1. Field of the Invention
The present invention relates to a high voltage switching circuit of a NAND type flash memory device and more specifically, to a high voltage switching circuit of a NAND type flash memory device to transfer a high voltage without a voltage drop.
2. Discussion of Related Art
A general high voltage switching circuit is configured as shown in FIG. 1 which is a circuit diagram illustrating the configuration of a high voltage switch circuit in a NAND type flash memory device by a conventional art.
Referring to FIG. 1, a high voltage pass transistor T101 transfers an input high voltage HVIN as being a high voltage HVOUT directly without a voltage drop. For the purpose of that, a pass voltage Vsel is applied to a gate of the high voltage pass transistor T101 so as to stably transfer the high voltage HVIN through the high voltage transistor T101.
A pass voltage generator 100 includes an input circuit 110 transferring a predetermined precharge voltage in response to an internal switching enable signal ENi, and a voltage boosting circuit 120 generating the pass voltage Vsel through a feedback loop using the precharge voltage, a clock signal CLK, and an external high voltage Vpp.
The input circuit 110 includes first and second inverters I101 and I102 buffering the internal switching enable signal ENi, and a first NMOS transistor N101 transferring an output of the second inverter I102.
The voltage boosting circuit 120 includes a pass node Q1 initiated by the precharge voltage and from which the pass voltage Vsel is generated, a diode D1 preventing an excessive boosting result for the pass voltage Vsel, a second NMOS transistor N102 transferring the external high voltage Vpp according to a voltage of the pass node Q1, a third NMOS transistor N103 transferring the voltage of the pass node Q1, which is transferred through the diode D1, according to a potential of the pass node Q1, and first and second capacitors C1 and C2 respectively boosting the voltage of the pass node Q1 and an output voltage of the second NMOS transistor N102 in response to the clock signal CLK. The voltage boosting circuit 120 may further include a third inverter I103 connected between an input terminal of the clock signal CLK and the first capacitor C1, and a fourth inverter I104 connected between an output terminal of the third inverter I103 and the second capacitor C2.
The pass voltage generator 100 outputs the pass voltage Vsel that is pumped up higher than the external high voltage Vpp by the operation with the first and second capacitors C1 and C2, in response to an inversed clock signal /CLK by the third inverter I103 and the non-inversed clock signal CLK by the fourth inverter I104, when the internal switching enable signal ENi is applied thereto.
Here, a potential of the pass node Q1, which has been raised higher through the pumping operation by the first capacitor C1, is further raised through the pumping operation by the second capacitor C2. Through the repetition of the pumping operations, the pass voltage Vsel of the pass node Q1 rises up to a target voltage.
Such a high voltage switching circuit of the NAND type flash memory device becomes difficult in assuring an efficient margin for a power source voltage gradually in accordance with a decrease of the power source voltage for operation. And, the high voltage switching circuit utilizes internal pumping capacitors by itself and obtains a gain by the number of stages of the pumping capacitors, transferring an input voltage as an output voltage without a voltage drop.
However, as the pumping capacitor of the high voltage switching circuit occupies very large circuit area therein, there is a limit to extending the number of the pumping stages regardless of a chip size. Therefore, there exists a need for another way to enhance the efficiency of the high voltage switching circuit without substantially affecting a chip size.